XC2S200-5FG456C

BGA, spartan-II, 2.5V, Field-Programmable Gate Array, Low-power, 56K

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Price:: US $10.78~11.25 / piece [Get Latest Price]

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	US $10.78~11.25

PartNumber:: XC2S200-5FG456C

Brand:: Xilinx, Inc - Xilinx | Pack: BGA | D/C: 03+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Total Price:: US $0

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Products Upload time: 2011-10-13

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Part Number:XC2S200-5FG456C
US $10.78 - 11.25
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Product Summary

The XC2S200-5FG456C is a spartan-II 2.5V FPGA. The XC2S200-5FG456C 2.5V Field-Programmable Gate Array gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S200-5FG456C offers densities ranging from 15,000 to 200,000 system gates, as shown in Table 1. System performance of the XC2S200-5FG456C is supported up to 200 MHz. Spartan-II devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined Virtex-based architecture.

Parametrics

XC2S200-5FG456C absolute maximum ratings: (1)VCCINT Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF Input reference voltage: –0.5 to 3.6 V; (4)VIN Input voltage relative to GND(3) 5V tolerant I/O(4): –0.5 to 5.5 V; (5)No 5V tolerance: –0.5 to VCCO+0.5 V; (6)VTS Voltage applied to 3-state output 5V tolerant I/O(4): –0.5 to 5.5 V; (7)No 5V tolerance: –0.5 to VCCO+0.5 V; (8)TSTG Storage temperature (ambient): –65 to +150℃; (9)TJ Junction temperature: +125℃.

Features

XC2S200-5FG456C features: (1)Low-power segmented routing architecture; (2)Full readback ability for verification/observability; (3)Dedicated carry logic for high-speed arithmetic; (4)Dedicated multiplier support; (5)Cascade chain for wide-input functions; (6)Abundant registers/latches with enable, set, reset; (7)Four dedicated DLLs for advanced clock control; (8)Four primary low-skew global clock distribution nets; (9)IEEE 1149.1 compatible boundary scan logic.